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OMAPL138EZWTD4 Discrete Semiconductor Devices NFBGA Digital Signal Processors

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OMAPL138EZWTD4 Discrete Semiconductor Devices NFBGA Digital Signal Processors
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Features
Specifications
Packaging Details: Standard / New / Original
L1 Cache Instruction Memory: 16 KB, 32 KB
L1 Cache Data Memory: 16 KB, 32 KB
Program Memory Size: 32 KB
Data RAM Size: 8 KB
Data ROM Size: 64 KB
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OMAPL138EZWTD4 Discrete Semiconductor Devices

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OMAPL138EZWTD4 Digital Signal Processors

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NFBGA Digital Signal Processors

Basic Infomation
Place of Origin: Philippines
Brand Name: Texas Instruments
Model Number: OMAPL138EZWTD4
Payment & Shipping Terms
Delivery Time: In stock
Payment Terms: L/C, D/A, D/P, T/T, Western Union, MoneyGram
Supply Ability: Contact us
Product Description

OMAPL138EZWTD4 / NFBGA-361 / Digital Signal Processors & Controllers - DSP, DSC

 

The OMAP-L138 C6000 DSP+ARM processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

 

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

 

The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

 

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

 

The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction and 16-KB data caches. Both caches are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core also has 8KB of RAM (Vector Table) and 64KB of ROM.

 

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32- KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

 

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardwarebased “root-of-trust,” the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and lets them securely set up the system and begin device operation with known, trusted code.

 

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, see the TMS320C674x/OMAP-L1x Processor Security User’s Guide.

 

Product Attribute Attribute Value
Texas Instruments
Product Category: Digital Signal Processors & Controllers - DSP, DSC
DSPs
OMAP-L138
OMAP
SMD/SMT
NFBGA-361
ARM926EJ-S, C674x
2 Core
456 MHz, 456 MHz
16 kB, 32 kB
16 kB, 32 kB
32 kB
8 kB
1.3 V
- 40 C
+ 105 C
Tray
Brand: Texas Instruments
Data Bus Width: 16 bit, 32 bit
Data ROM Size: 64 kB
Height: 0.94 mm
I/O Voltage: 1.8 V, 3.3 V
Instruction Type: Fixed/Floating Point
Interface Type: I2C, Parallel, SPI, USB
Length: 13 mm
MFLOPS: 2746 MFLOPS
Moisture Sensitive: Yes
Number of Timers/Counters: 3 Timer
Processor Series: OMAP
Product Type: DSP - Digital Signal Processors & Controllers
Factory Pack Quantity: 90
Subcategory: Embedded Processors & Controllers
Supply Voltage - Max: 1.35 V
Supply Voltage - Min: 1.25 V
Watchdog Timers: Watchdog Timer
Width: 13 mm
Unit Weight: 0.027845 oz

 

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